Browse Prior Art Database

Functional Memory Cell

IP.com Disclosure Number: IPCOM000075724D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Wiedmann, SK: AUTHOR

Abstract

This associative-memory cell employs diodes D1 and D2 coupling the cell to the bit lines 12 and 16, respectively. Data is read out of the cell by the application of a pulse to the read/write word line 10 causing the read transistor T5 to conduct current to the search/read line 16 if transistor T3 has been turned on. If transistor T4 has been turned on there will be no current in the search/read line. To write data in the storage cell one of the bit lines 12 or 14 is lowered simultaneously with the raising of the potential on the word line 10. For instance, if a "1" is to be stored in the cell, bit line 12 is lowered turning off transistor T4 and allowing transistor T3 to conduct. While if a "0" is to be stored in the cell, bit line 14 is lowered turning off transistor T3 and causing transistor T4 to conduct.

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Functional Memory Cell

This associative-memory cell employs diodes D1 and D2 coupling the cell to the bit lines 12 and 16, respectively. Data is read out of the cell by the application of a pulse to the read/write word line 10 causing the read transistor T5 to conduct current to the search/read line 16 if transistor T3 has been turned on. If transistor T4 has been turned on there will be no current in the search/read line. To write data in the storage cell one of the bit lines 12 or 14 is lowered simultaneously with the raising of the potential on the word line 10. For instance, if a "1" is to be stored in the cell, bit line 12 is lowered turning off transistor T4 and allowing transistor T3 to conduct. While if a "0" is to be stored in the cell, bit line 14 is lowered turning off transistor T3 and causing transistor T4 to conduct. For a search, the potential of the search/read line 16 is lowered with respect to the read/write select line 10. If transistor T3 is in the on state, all the load current will flow into the base of transistor T4 and cause a large current on the read/write sense line 18 indicating a mismatch. On the other hand, if transistor T4 is conducting there will be no current flowing in transistor T5 when the pulse is applied to the search/read line 16.

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