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Monolithic Associative Memory Cell

IP.com Disclosure Number: IPCOM000075725D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Wiedmann, SK: AUTHOR

Abstract

This storage cell can be associatively searched. To associatively search the memory one of the bit lines B0 or B1 is lowered. This causes the input/output transistors T3 or T4 connected to the lowered bit line to conduct to give a no-match input to the associative sense amplifier 28 if it is connected to the nonconducting one of two transistors T1 or T2, and it causes that transistor T3 or T4 to remain nonconducting to give a match signal to associative sense amplifier 28 if it is connected to the conducting one of the two cross-connected transistors.

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Monolithic Associative Memory Cell

This storage cell can be associatively searched. To associatively search the memory one of the bit lines B0 or B1 is lowered. This causes the input/output transistors T3 or T4 connected to the lowered bit line to conduct to give a no- match input to the associative sense amplifier 28 if it is connected to the nonconducting one of two transistors T1 or T2, and it causes that transistor T3 or T4 to remain nonconducting to give a match signal to associative sense amplifier 28 if it is connected to the conducting one of the two cross-connected transistors.

To read the data out of the storage cell, the word driver 22 raises the bit line W/L so as to cause Node A and B to rise. This causes the transistors T3 or T4 connected to the collector of the nonconducting one of transistors T1 and T2 to conduct and put a signal on the bit line B1 or B0 associated therewith, to be sensed by either the B1 or B0 sense amplifiers 26 or 24.

To write data into the storage cell, the word line W/L is again raised by the word driver 22. Simultaneously, the potential on one of the bit lines B0 or B1 is decreased by the B0 bit driver 24 or B1 bit driver 26, causing the transistor T3 or T4 to conduct and reduce the potential at node A or node B until the transistor T1 or T2 (with its base directly connected to that node) is biased off and the other transistor is biased on.

The cell is fabricated as shown in the monolithic layout, where the bases for transis...