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Precise Interrupt Mechanism for a High Speed Computer

IP.com Disclosure Number: IPCOM000075727D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Senzig, DN: AUTHOR

Abstract

The described technique enables high-speed machines to provide precise interrupt information. At each store instruction, the CPU stores all visible registers in one or more auxiliary storage devices. In an IBM System/360 CPU, the visible registers are the program status words, general purpose registers, and floating point registers. Between store instructions, the CPU runs as rapidly as possible with as much overlap as possible. If an interrupt occurs between store instruction i and store instruction i+1, the CPU uses the information stored during the execution of store instruction i to restart with store instruction i. The CPU runs in a manner that permits precise identification of the cause of the interrupt when it reoccurs. This will probably be the completely sequential execution of the instructions between the stores.

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Precise Interrupt Mechanism for a High Speed Computer

The described technique enables high-speed machines to provide precise interrupt information. At each store instruction, the CPU stores all visible registers in one or more auxiliary storage devices. In an IBM System/360 CPU, the visible registers are the program status words, general purpose registers, and floating point registers. Between store instructions, the CPU runs as rapidly as possible with as much overlap as possible. If an interrupt occurs between store instruction i and store instruction i+1, the CPU uses the information stored during the execution of store instruction i to restart with store instruction i. The CPU runs in a manner that permits precise identification of the cause of the interrupt when it reoccurs. This will probably be the completely sequential execution of the instructions between the stores. In essence, there is no restriction between the parallel issuing or execution of any instruction, except a store instruction, nor is it necessary to mark a trail of branch instructions.

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