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Memory Cell with Low Standby Power

IP.com Disclosure Number: IPCOM000075733D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Wiedmann, SK: AUTHOR

Abstract

This cell may be operated at low-standby power and powered up very rapidly for reading and writing operations.

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Memory Cell with Low Standby Power

This cell may be operated at low-standby power and powered up very rapidly for reading and writing operations.

Reading is performed by applying a negative address pulse to the word line 10 causing the diodes D1 and D2 to be forward biased. This results in a voltage differential between the bit lines 12 and 14 that is a function of the different potentials at the cell nodes C1 and C2. A differential amplifier across the bit lines can, therefore, indicate the state of the cell. Cell drive current is increased during this address period by supplying a large current through the bit lines 12 and 14. This current is independent of the standby current supplied through the load devices T3 and T4 from the power line 16. By powering up the cell in this manner for reading, faster operating times are obtained.

Writing is performed by applying a negative pulse to the word line and supplying increased current to only one of two bit lines 12 or 14. If a "0" is to be stored the bit line B0 is powered up to turn device T1 on and if a "1" is to be stored bit line B1 is powered up to cause device T2 to conduct.

As shown in the cell layout, diodes D1 and D2 are realized by using the P+N+ junction of a transistor. The beta of these transistors has been killed by applying a P+ isolation diffusion under the N+ emitter area.

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