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Browse Prior Art Database

By Passable Shift Register

IP.com Disclosure Number: IPCOM000075764D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

diGleria, PA: AUTHOR [+2]

Abstract

This multilevel arrangement of gates allows the bypassing of one or several stages of the shift register without increasing the shift delay. The shift register performs conventional shifting in one mode of operation and can be used as an address register in another mode of operation. The provision of bypassing certain stages of the register enhances yield improvement, or allows dynamic recovery when used in connection with array-like structures.

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By Passable Shift Register

This multilevel arrangement of gates allows the bypassing of one or several stages of the shift register without increasing the shift delay. The shift register performs conventional shifting in one mode of operation and can be used as an address register in another mode of operation. The provision of bypassing certain stages of the register enhances yield improvement, or allows dynamic recovery when used in connection with array-like structures.

Registers Sn-1, Sn, etc. form a conventional shifting chain and are also used to address array lines. In error-free condition, all gates are deselected. If, as an example, register Sn or its associated array line is faulty, gate G12 is energized, thus bypassing stage Sn. If both Sn and Sn+1 registers are faulty, gate G23 will also be energized whilst the registers containing the errors will be deselected. The number of adjacent stages that can be bypassed depends on the gating levels provided. However, the stage-to-stage delay is independent of the number of bypassed registers, since each active path encounters only one gate.

The control of activating gates and deactivating registers, not shown, assumes that the error associated with a register has been located and stored in the system.

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