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Multiply/Divide Unit for a High Performance Digital Computer

IP.com Disclosure Number: IPCOM000075783D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 4 page(s) / 48K

Publishing Venue

IBM

Related People

Bratun, JM: AUTHOR [+5]

Abstract

The figure presents a multiply/divide unit for a high performance computer. Multiplication is accomplished in the following manner. The Multiplier Selector scans the Multiplier Register, gating a new group of bits to the Multiplier Decoder each iteration. The Multiplier Decoder and Multiple Gates, convert 6 multiples of the multiplicand into 3 multiples which are properly aligned at the input of CSA-A. CSA-A adds the 3 multiples, forming a partial product in sum and carry form.

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Multiply/Divide Unit for a High Performance Digital Computer

The figure presents a multiply/divide unit for a high performance computer. Multiplication is accomplished in the following manner. The Multiplier Selector scans the Multiplier Register, gating a new group of bits to the Multiplier Decoder each iteration. The Multiplier Decoder and Multiple Gates, convert 6 multiples of the multiplicand into 3 multiples which are properly aligned at the input of CSA-A. CSA-A adds the 3 multiples, forming a partial product in sum and carry form.

The first partial product is added to "zero" in CSA-B and CSA-C (i.e., initially the outputs of the two right shifters are zero). The first partial product is then shifted to the right 6 bits to be in alignment with the second partial product. CSA- B and CSA-C continue to accumulate partial products until the entire multiplier has been scanned. The final product, in sum and carry form is then gated into the Product Sum and Product Carry registers. The six sum and carry bits shifted out of CSA-C each iteration are added in the Spill Adder. The primary function of the Spill Adder is to propagate a carry bit forward to the least significant bit of the final product at CSA-C. Also, low-order product bits, which are added in the Spill Adder, can be stored in the Spill Register when required by the multiple instruction.

The division technique utilized is an extension of the basic one quotient bit per iteration nonrestoring division operation, which has been used in slower computers. The one quotient bit method is an implementation of the recursion equation. R(i+1) = 2 (R(i) - Q(i)D) (1)

where R(i) = i th remainder

R(o) = dividend in fraction form (x bits in length)

D = divisor in fraction form (y bits in length)

Q(i) = i th quotient bit

+1 if R(i) >/- 0

-1 if R(i) < 0.

Assuming that x > y, a hardware savings is obtained by bit normalizing, since this will insure that no R(i) will have more significant bits than R(o). Theoretically, it is seen that 6 quotient bits per iteration can be generated by implementing the recursion equation, R(i+1) = 64 (R(i) - Q(i) D)

where R(i) = ith remainder (2)

R(o) = dividend in fraction form

D = divisor in fraction form

Q(i) = i th subset of 6 quotient bits.

However, there are some unique problems encountered in the implementation of this equation. First, how is equation (2) implemented by the hardware of the figure? Second, how is Q(i) selected and what are the specifications for D, which will insure that all R(i) will have the minimum possible length?

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R(i+1) in equation (2) can be generated in sum and carry form by adding a six-bit left shifter to each CSA-C output. The multiplication, -64Q(i) D, can be performed in one pass through the Multiple Gates and CSA-A. Since a is a six-bit number, -Q(i) is designated as the multiplier, and 64D is the multiplicand. R(i), the result of the previous iteration, is in sum and carry form, and can be shifted left 6 bits...