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Phase Lock Loop with Constant Duty Cycle

IP.com Disclosure Number: IPCOM000075797D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 35K

Publishing Venue

IBM

Related People

Niccore, FW: AUTHOR

Abstract

The function of this circuit is to generate a periodic output waveform whose period is the same as the period between pulses in the input waveform, and further where the output periodic waveform is always divided into a 75% portion of one polarity and a 25% portion of another polarity, irrespective of changes in the period. The choice of 75% and 25% is optional; the output waveform may be apportioned in any desired manner depending upon the choice of reference voltages used in the circuit.

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Phase Lock Loop with Constant Duty Cycle

The function of this circuit is to generate a periodic output waveform whose period is the same as the period between pulses in the input waveform, and further where the output periodic waveform is always divided into a 75% portion of one polarity and a 25% portion of another polarity, irrespective of changes in the period. The choice of 75% and 25% is optional; the output waveform may be apportioned in any desired manner depending upon the choice of reference voltages used in the circuit.

In operation, capacitor 10 is constantly being charged by current from transistor 12. The amount of current flowing through transistor 12 controls the charge rats of capacitor 10. Each time an input data pulse arrives at transistor 14, capacitor 10 is discharged to ground through resistor 16 and transistor 14. Thus the voltage at node 18 is a sawtooth waveform, with a periodicity the same as the input pulse periodicity. The sawtooth waveform is passed by the emitter follower configuration 20 to one input of comparator 22. The other input to comparator 22 is a reference voltage derived from a voltage dividing network 24 made up of diodes. The voltage dividing network can be made very accurate in a monolithic circuit; where the voltage drop across each diode is almost identical due to inherent matching typical of monolithic circuits.

Comparator 22 will have an output each time the sawtooth waveform from node 18 rises above the reference voltage fed back from diodes 24. This produces the output signal.

The output signal is low-pass filtered and monitored by the differential DC amplifier 26 to generate a DC error signal, which is fed back to the base of transistor 12 to control the charge rate of capacitor 10.

The monitoring is accomplished by amplifying the output signal with transistor 28 and fixing its amplitude to the voltage drop across four diodes 27. The diodes 27 are identical to the diodes 24, so that the amplitude of the output signal will...