Browse Prior Art Database

Communication Line Microcontroller

IP.com Disclosure Number: IPCOM000075827D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 4 page(s) / 89K

Publishing Venue

IBM

Related People

Froemke, JW: AUTHOR [+3]

Abstract

The microcontroller 4 is provided to sequentially execute microinstructions read from control storage 12. Microcontroller 4 and control storage 12 are parts of a multiple line terminal adapter 5 (MLTA) which provides an interface between a synchronous I/O channel 6 connected with a CPU 7 (central processing unit of the IBM System/3 type, for example) and a plurality of transmission lines L.

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Communication Line Microcontroller

The microcontroller 4 is provided to sequentially execute microinstructions read from control storage 12. Microcontroller 4 and control storage 12 are parts of a multiple line terminal adapter 5 (MLTA) which provides an interface between a synchronous I/O channel 6 connected with a CPU 7 (central processing unit of the IBM System/3 type, for example) and a plurality of transmission lines L.

The microprograms located in storage 12 consist of a series of microinstructions arranged in routines to service Data, Start I/O, (SI/O) and Time Out service requests, and for the following operations in particular: a) decode and execution of SI/O instructions, b) I/O interrupt requests, c) I/O cycle steal requests, d) main storage addressing (main storage of CPU 7), e) data formatting, f) length count incrementing, g) status and diagnostic byte generation,
h) line time outs, and i) transmission error checking.

Microcontroller 4 addresses the correct microinstruction in control storage 12 and executes the instruction. Execution usually involves reading data from one of a line's HDB's 14 (high density buffers), modifying the data in some way (depending upon the particular op-code), and storing the modified data back into the HDB's 14. Other instruction executions may involve testing specified signals, etc. The op-codes are contained in control store 12. There may be a series of the HDB's 14 and they can be loaded with a Load I/O (LI/O) instruction or they can be loaded by the microcontroller 4 itself. Eight different communication lines L may be controlled all at once; and each of these lines L is a logical unit by itself and each contains sixteen of the HDB buffers 14, each of which is eight bits in length. The HDB's 14 can contain the following information: branch to addresses, addresses of storage in CPU 7 in which to store and fetch data, condition information for microcontroller 4, and the type of lines L which are being controlled.

Microcontroller 4 includes ALU 16 (arithmetic logic unit) and data from two sources (K and Y) can be merged in various ways to produce the desired result. The operation to be performed is specified by using four control lines 18 and includes a logical OR, and logical AND, and an Exclusive OR operation. The accumulate register 20 is fed by the ALU 16 and provides a concentrator of signals on microcontroller 4. ALU 16 provides two inputs 24 and 26 to accumulator 20, one being a normal input and the other providing a shift left function. The third input 28 to register 20 is from the Data Bus Out (DBO) register 30 and allows data to be used in load I/O instructions. The DBO register 30 contains data which has been sent to the MLTA 5 on the channel DBO. The fourth input to register 20 is the output of the micro-instruction address registers low (MIAR-LO) 32. The MIAR-LO 32 addresses the eight low-order bits of control store 12, while the MIAR-HI 54 addresses the two upper bits of co...