Browse Prior Art Database

Multiple Communication Line Bit Time Scanner

IP.com Disclosure Number: IPCOM000075828D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 74K

Publishing Venue

IBM

Related People

Bennett, WA: AUTHOR [+3]

Abstract

The scanner provides transmit/receive simultaneous clocking for a plurality of independently operating, asynchronous communication lines 10. It also detects valid start bits and clear-to-send signals during the receive and transmit operations, respectively.

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Multiple Communication Line Bit Time Scanner

The scanner provides transmit/receive simultaneous clocking for a plurality of independently operating, asynchronous communication lines 10. It also detects valid start bits and clear-to-send signals during the receive and transmit operations, respectively.

The communication lines 10 are scanned in sequence by the scanner. A character on a communication line 10 is shown in Fig. 1. During receiving, the reception of a valid start bit on any of the communication lines 10 and on line 14 requires that a space level be present on that line 10 continuously for at least one-half of an ideal bit time. When a valid start bit has been received, the bit scanner provides a bit-time strobe pulse 16 for the remaining eight bits of the character and occurring in the center of each bit time. Other circuitry, not shown, is controlled by the bit time strobe pulse 16 to actually sample lines 10. The scanner thus provides proper timing for examining an incoming character bit-by- bit in the center of each bit, and provides proper timing to transmit a character out on a line 10 to a terminal and insure that the bits of the character are clocked at the proper rate. When a stop bit on a line 10 has been received, the scanner then begins searching for a new start bit.

Selection of a particular transmission line 10 and of one of the controlling oscillators 26 and 28 is accomplished by line selection counter 30, along with line decode logic 32. Counter 30 is incremented by the clock of the associated Central Processing Unit (CPU), and a particular output line of decode logic 32 denotes the particular line 10 which has been selected for a particular scan using the corresponding line logic 11. A scan is the period during which the scanner is working on a particular line 10 and includes a receive subscan and a transmit subscan, each for one-half of the full scan.

The lowest-order bit of counter 30 denotes a receive subscan (bit = 0) and a transmit subscan (bit = 1). This bit controls the outputs of oscillators 26 and 28 so that the particular oscillator 26 or 28 is used which corresponds with the data rate of the particular terminals attached to lines 10. The remaining three higher- order bits of counter 30 are decoded into the eight lines 34 connected with line logic 11, to select a particular line 10 for a bit scan. The output lines of counter 30 also address a particular nine-bit word in high-density buffer (HDB) storage 36, which is a read-write storage used to record a nine-bit word representing the condition of both the receive and transmit subscan for each line 10. This word contains information about the particular line 10 which was stored in the HDB 36 the last time the line was scanned. After a start bit has been received on a particular line 10, counter 38 continues...