Browse Prior Art Database

Bubble Domain Decoder with Built In Memory

IP.com Disclosure Number: IPCOM000075845D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Keefe, GE: AUTHOR [+3]

Abstract

Existing bubble domain decoders and switching gates use control windings to inhibit or create a preferential bubble position at a correct time. These techniques have high-power dissipation and stringent timing requirements, because the proper address current levels must be maintained in the control loops for the entire duration of the memory cycle in order to read/write the entire block of information. The techniques shown here provide a lower power decoding scheme having a built-in memory for the input addresses.

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Bubble Domain Decoder with Built In Memory

Existing bubble domain decoders and switching gates use control windings to inhibit or create a preferential bubble position at a correct time. These techniques have high-power dissipation and stringent timing requirements, because the proper address current levels must be maintained in the control loops for the entire duration of the memory cycle in order to read/write the entire block of information. The techniques shown here provide a lower power decoding scheme having a built-in memory for the input addresses.

This decoder uses a strip line and a pair of idlers to control domain movement between one of two channels. Permalloy elements 10 are located on magnetic sheet 12 which could be orthoferrite or garnet, for instance. Under the action of the rotating in-plane magnetic field H, such domains propagate to pole position 1 of Tibar element 14. When H rotates to direction 2, the domain, has two possible paths: pole position 2 on element 16 and pole position 2' on element
14. However, pole position 2 on element 16 is always preferred because of its proximity to pole position 1, unless another domain is trapped at pole position 1' of idler A. Therefore, the presence or absence of a domain in idler A determines the information being transferred from track A to tracks C or B. The reference domain in the idlers A and B is shifted back and forth between these idlers by energizing strip line C.

Similar logic functions can als...