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Asymmetrical High Speed Storage

IP.com Disclosure Number: IPCOM000075872D
Original Publication Date: 1971-Dec-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Paddock, RC: AUTHOR [+3]

Abstract

High-performance computer systems use a hierarchy storage system consisting of a high-speed low-capacity buffer storage BS with a slower speed high-capacity backing or main store MS. MS may be logically divided into equal size blocks which are the units of transfer between BS and MS. In an exemplary system using 24-bit addressing and a block size of 64 bytes, MS can be logically divided into 218 blocks with the high-order 18 bits of the address representing the block number and the remaining 6 bits the block displacement, i.e., the byte within the block. BS may also be logically divided into blocks, corresponding in size to the blocks of MS.

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Asymmetrical High Speed Storage

High-performance computer systems use a hierarchy storage system consisting of a high-speed low-capacity buffer storage BS with a slower speed high-capacity backing or main store MS. MS may be logically divided into equal size blocks which are the units of transfer between BS and MS. In an exemplary system using 24-bit addressing and a block size of 64 bytes, MS can be logically divided into 218 blocks with the high-order 18 bits of the address representing the block number and the remaining 6 bits the block displacement, i.e., the byte within the block. BS may also be logically divided into blocks, corresponding in size to the blocks of MS. Associated with BS is a directory array, each entry of which corresponds to a block location in BS and contains the block number identifying the block of MS currently residing in the associated block location of BS. The degree of associativity of BS determines how many block locations of BS a given block of MS can be mapped into. If a given block of MS can be mapped into any one of the blocks of BS, then BS is fully associative and the degree of associativity is equal to the block capacity of BS; if the given block can be mapped into one and only one block of BS, then BS is nonassociative and the degree of associativity is equal to one; if the given block can be mapped into any one of a set of blocks of BS, where a set may consist of two or more blocks but less than the block capacity of BS, then BS is set associative and the degree of associativity is greater than one but less than the block capacity of BS. Thus, an N-way set-associative BS allows a given block of MS to be mapped into any of N blocks comprising a set within BS. An N-way set-associative BS can be further divided into N nonassociative sectors, each having a directory array associated with it. If the block capacity of each sector is equal, BS is considered a symmetric device. An alternative to the symmetric device is one in which the sectors are not of equal size and, therefore, is considered to be an asymmetric device.

An exemplary 3-way asymmetric set-associative BS is shown having a 16K byte capacity. Sector A has a capacity of 8K bytes, Sector B a capacity of 4K bytes and Sector C a capacity of 4K bytes. Additionally, Sector A is divided into 128 blocks with each block consisting of 16 full words. Accordingly, 7 bits of the address are used to identify a unique block within the sector and 4 bits to identify the word within the selected block. Sectors B and C are each divided into 64 blocks with each block consisting of 16 full words, as in Sector A, requiring only 6 bits of the address to identify a unique block within these sectors. Associated with Sectors A, B and C are Directory Arrays A, B and C each having a number of entries equal to the number of blocks in the associated sectors.

In operation, when the Central Processing Unit (CPU) requires a fetch from storage, the directory arrays A,...