Browse Prior Art Database

Time Division Multiplex Modulator for Multiphase Dynamic FET Logic

IP.com Disclosure Number: IPCOM000075887D
Original Publication Date: 1971-Dec-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Rutherford, DH: AUTHOR

Abstract

This circuit allows the time sharing of integrated circuit wiring paths and chip signal input/output pads, improving diagnostic access and doubling the effective chip "signal I/O to circuit ratio".

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Time Division Multiplex Modulator for Multiphase Dynamic FET Logic

This circuit allows the time sharing of integrated circuit wiring paths and chip signal input/output pads, improving diagnostic access and doubling the effective chip "signal I/O to circuit ratio".

The modulator circuit utilizes eight FET devices Q1 to Q8. In this 40 dynamic FET logic family, signal inputs A and A are valid logical complements during phase times 01 and 02. Signal inputs B and B are valid logical complements during phase times 03 and 04.

During 01 time, the output capacitance CO is charged via Q1 and Q2 if A is a logical 1. CO is discharged via Q3 and Q4 if A is a logical 1. The charge on CO controls device Q9 to allow the signal A to be provided at the output of device Q10 during 02 time.

During 03 time CO is charged via Q5 and Q6 if B is a logical 1. CO is discharged via Q7 and Q8 if B is a logical 1. The charge on CO controls device Q11 to allow the signal B to be provided at the output of device Q12 during 04 time.

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