Browse Prior Art Database

Up/Down Decimal Counter With Clear and Preload

IP.com Disclosure Number: IPCOM000075888D
Original Publication Date: 1971-Dec-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Brittain, JE: AUTHOR

Abstract

Binary coded decimal (BCD) inputs are used directly to preload BCD counter stages, with decoder logic circuitry converting the counter contents to a single line output.

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Up/Down Decimal Counter With Clear and Preload

Binary coded decimal (BCD) inputs are used directly to preload BCD counter stages, with decoder logic circuitry converting the counter contents to a single line output.

The counter uses two BCD 4-bit bidirectional counters 10 and 11, with 10 arranged to count units and 11 counting tens. If a negative signal is applied to the "count up" line 14, 10 will advance one count whereas a negative signal applied to the "count down" line 15, 10 will recede one count. The tens counter 11 will advance with each negative carry signal from the lower digit counter 10 on line 17, or will recede with a negative borrow signal on line 18 from 10.

BCD inputs 19 and 20 are coded to any predetermined equivalent decimal number from 0 to 99 in the example shown. The desired inputs 19 and 20 as positive signals will load into 10 and 11 at any time that preload line 21 goes negative. The BCD-to-decimal decoders 24 and 25 will accept a BCD positive coded signal from 10 and 11, respectively. One output U0 - U9 of 24 and one output T0 - T9 of 25 will go negative in response to the 10 and 11 outputs.

Output logic 30 uses a multiplicity of two-way Nand logic blocks such as 31, 32 and 33 to produce a single positive output signal 0 - 99, in response to any combination of two negative signals from 24 and 25 for the desired decimal output. A clear signal at terminal 22 can return the counter to 0. Normally, a count up signal after a 99 count will rec...