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Offset Register

IP.com Disclosure Number: IPCOM000075923D
Original Publication Date: 1971-Dec-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Wetzel, JA: AUTHOR

Abstract

A dynamic address translation technique, using a nonassociative directory look-aside table (DLAT) together with a single offset register, provides an effective cost/performance trade off between nonassociative and two-way set associative symmetric DLATS. The nonassociative DLAT combined with the single offset register functions as a two-way set associative DLAT and, since the sectors of the device are not of equal size, the combined DLAT is considered to be asymmetric.

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Offset Register

A dynamic address translation technique, using a nonassociative directory look-aside table (DLAT) together with a single offset register, provides an effective cost/performance trade off between nonassociative and two-way set associative symmetric DLATS. The nonassociative DLAT combined with the single offset register functions as a two-way set associative DLAT and, since the sectors of the device are not of equal size, the combined DLAT is considered to be asymmetric.

In dynamic address translation, a CPU provided virtual page address (VPA) is translated to the real page address (RPA) for each storage fetch or store operation. Translation involves a series of table look-up operations which are time consuming. To minimize the table look-up operation, the look-aside register array, DLAT, is provided, each entry of which contains the VPA and corresponding RPA of the most recently translated addresses. For each storage reference, a portion of the CPU provided VPA is used to access an entry in the nonassociative store which is applied to compare circuit 2. At the same time, the VPA entry of the offset register is applied to the compare circuit 4. The CPU provided VPA is then compared with the VPA entry in the nonassociative store and the offset register. If either compare circuit 2 or compare circuit 4 detects a comparison, AND circuit 6 or AND circuit 8 is enabled, respectively, to gate the associated ~PA from the nonassociative store or the offset r...