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Decode Matrix

IP.com Disclosure Number: IPCOM000075943D
Original Publication Date: 1971-Dec-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Gersbach, JE: AUTHOR

Abstract

The drawing shows two decoders 11, 12 driving a matrix of final decode circuits 13. Transistor T1 is the selection transistor which is selected when there is current provided to its emitter and its base is more positive than the base of any other transistor, whose emitter is connected to the same X line. Current I1 thus is routed to the base of transistor T2, turning T2 on and causing the output to rise. When the output reaches 2 volts (the reference for the Y decode output), transistor T4 will conduct and the current of transistor T1 will switch to transistor T4. Transistor T2 will then begin to turn off and decay to a value sufficient to supply the DC base current for transistor T3. At the end of the timing pulse, current I1 will switch out of node XN and into node Z to provide off drive for transistor T3.

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Decode Matrix

The drawing shows two decoders 11, 12 driving a matrix of final decode circuits 13. Transistor T1 is the selection transistor which is selected when there is current provided to its emitter and its base is more positive than the base of any other transistor, whose emitter is connected to the same X line. Current I1 thus is routed to the base of transistor T2, turning T2 on and causing the output to rise. When the output reaches 2 volts (the reference for the Y decode output), transistor T4 will conduct and the current of transistor T1 will switch to transistor T4. Transistor T2 will then begin to turn off and decay to a value sufficient to supply the DC base current for transistor T3. At the end of the timing pulse, current I1 will switch out of node XN and into node Z to provide off drive for transistor T3. The output off drive can be provided by another diode from Z to the output or by independent means. This circuit can tolerate a very poor PNP transistor (T2) and still provide high performance at low power compared to an all NPN matrix.

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