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Four Phase Dynamic Polarity Hold Latch

IP.com Disclosure Number: IPCOM000075952D
Original Publication Date: 1971-Dec-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Radzik, LC: AUTHOR

Abstract

The diagram is a polarity-hold (PH) latch circuit comprised of fieldeffect transistors, (FET's) operating in a four-phase dynamic configuration. This type of PH latch is one in which the output signal will be maintained at a set value so long as a control input is maintained at a holding level, and will be freed to correspond to an input signal whenever the control input is released.

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Four Phase Dynamic Polarity Hold Latch

The diagram is a polarity-hold (PH) latch circuit comprised of fieldeffect transistors, (FET's) operating in a four-phase dynamic configuration. This type of PH latch is one in which the output signal will be maintained at a set value so long as a control input is maintained at a holding level, and will be freed to correspond to an input signal whenever the control input is released.

The latch is driven and clocked from a power supply having four non- overlapping phases and is comprised of circuit blocks, as shown in Fig. 1. In the block, voltage will be applied during a first phase to a lead 1 and current will pass through FET 2 to charge a capacitance 3 on the output lead 4. Capacitance 3 will normally be the input capacitance of the FET's of the next logic block and is not formed as a separate capacitive circuit. On the next phase, lead 5 receives a voltage to make FET 6 conductive. If at this time, any input lead 7, 8 or 9 has previously received a voltage signal and charged the input capacitance of its FET 10, 11 or 12 so that the FET is conductive, then capacitance 3 will be discharged, and output 4 will remain at a low voltage for the third and fourth phases to indicate that an input lead was at a control voltage. This sequence will be repeated for each series of four-clock pulses so that the output lead 4 during phases 3 and 4 is the complement of the OR of the inputs 7, 8 and 9.

Fig. 2 shows the assembly of four of such circuit blocks into a PH latch. In the latch circuit, a circuit block is given a phase number corresponding to the clock phase at which the control leads such as 5, 7, 8 and 9 have valid signals thereon. It is assumed here that the latch data input lead 15 and the control lead 16...