Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Read Only Memory

IP.com Disclosure Number: IPCOM000075968D
Original Publication Date: 1971-Dec-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 4 page(s) / 71K

Publishing Venue

IBM

Related People

Jordan, PV: AUTHOR [+3]

Abstract

This circuit relates to read-only stores where the storage elements are transistors arranged in an array or matrix. For example, a "1" bit may be indicated by a transistor which is "on", and a "0" bit will then be indicated by a transistor which is "off".

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 47% of the total text.

Page 1 of 4

Read Only Memory

This circuit relates to read-only stores where the storage elements are transistors arranged in an array or matrix. For example, a "1" bit may be indicated by a transistor which is "on", and a "0" bit will then be indicated by a transistor which is "off".

Since a 0 bit is indicated by a transistor which is off, the transistor may be unconnected and seemingly may be eliminated from the circuit, except that it may be required in a different application for a different data pattern. The latter may contain all 1 bits in any row, and, therefore, the prior art transistor matrix must include a full array of transistors to take care of any possible pattern of bits to be stored. That is, in integrated circuitry a so-called master-slice is produced, which includes a full array of transistors of which only some are connected in any particular application. Memories in accordance with the prior art, therefore, included many unused and unconnected transistors each corresponding to, for example, a 0 bit.

In this circuit a read-only memory is provided in which only half of the number of transistors is required for each row of the matrix, compared to the prior art. This is achieved by forming the complement of all rows having a 1 bit in more than half the bit locations. Upon readout, an inverter again complements the inverted row.

Assume that it is desired to store the following data pattern in a 4 x 4 storage matrix: E F G H

A 0 1 0 1

B 0 1 1 0

C 1 0 1 1

D 0 1 1 1.

It will be seen that in rows C and D a majority of the entries are 1 bits. Taking the complements of rows C and D the matrix becomes: E F G H

A 0 1 0 1

B 0 1 1 0

C 0 1 0 0

D 1 0 0 0.

This matrix may be stored in the manner shown in the drawing. Terminals E, F, G, H represent the output of a column select decoder, not shown. Switches S1 to S16, inclusive, may open or close according to the data in store to disconnect or connect terminals E, F, G, H to the respective bases of array transistors 11, 12, 21, 22, 31, 32, 41, 42. The collectors of the array transistors are connected to ground, and their emitters are connected to the collectors of transistors 1, 2, 3, 4 in the manner shown.

Column E of the complemented matrix contains a 1 bit only in the fourth row. Switch S4 is closed and switches S1, S2, and S3 are open. The terminal E is,

1

Page 2 of 4

therefore, connected only to the base of transistor 41. Column F contains 1 bit entries in the first, second, and third rows. Switches S5, S6, and S7 are closed and switch S8 is open. The terminal F is, therefore, connected to the bases of transistors 11, 21, and 31. Column G of the matrix contains a 1 bit only in the second row. Switch S10 is closed and switches S9, S11, and S12 are open. The terminal G is, therefore, connected to the base of transistor 22. Column H contains a 1 bit only in the first row. Switch S13 is closed and switches S14, S15, and S16 are open. Therefore, the terminal H is connected to the base of trans...