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Browse Prior Art Database

Phase Detector for Self Clocking Variable Frequency Oscillators

IP.com Disclosure Number: IPCOM000075993D
Original Publication Date: 1971-Dec-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Johnson, HW: AUTHOR

Abstract

This phase detector is used in systems wherein the presence of a given data bit is random within a train of data pulses, and in which the pulse train is not initially at the same frequency and phase as a voltage-controlled oscillator (VCO) 10. The phase detector must change the frequency and phase of the VCO into synchronization with that of the data signal. In operation, AC flip-flop 13 is set by the data signal 11 and reset by a clock signal 12, which is the positive phase of the VCO signal. The output signal 14 from flip-flop 13 is proportional to the phase difference between the data and the clock signals 11 and 12, respectively, and is applied as a control signal to gate current source 15. It is also applied to the D input of flip-flop 18, which responds at the following clock time and captures the data bit detected.

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Phase Detector for Self Clocking Variable Frequency Oscillators

This phase detector is used in systems wherein the presence of a given data bit is random within a train of data pulses, and in which the pulse train is not initially at the same frequency and phase as a voltage-controlled oscillator (VCO)
10. The phase detector must change the frequency and phase of the VCO into synchronization with that of the data signal. In operation, AC flip-flop 13 is set by the data signal 11 and reset by a clock signal 12, which is the positive phase of the VCO signal. The output signal 14 from flip-flop 13 is proportional to the phase difference between the data and the clock signals 11 and 12, respectively, and is applied as a control signal to gate current source 15. It is also applied to the D input of flip-flop 18, which responds at the following clock time and captures the data bit detected. The output signal from flip-flop 18 is ANDed with the negative phase of the VCO output 24 to generate a reference signal 25, which is then used to gate current source 16. AND gate 19 provides only one reference pulse for each data pulse. Current sources 15 and 16 are complementary and provide currents of the same magnitude but of opposite polarity. As current source 15 is gated ON, integrating capacitor 17 charges to a voltage proportional to the phase difference between signals 11 and 12. As current source 16 is gated ON, integrating capacitor 17 discharges by a fixed or reference...