Browse Prior Art Database

Memory Address Sync and Stop Controller

IP.com Disclosure Number: IPCOM000075994D
Original Publication Date: 1971-Dec-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Medal, LH: AUTHOR

Abstract

The device provides sync capability and program stop control for a digital system.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 79% of the total text.

Page 1 of 2

Memory Address Sync and Stop Controller

The device provides sync capability and program stop control for a digital system.

As seen in the drawing, memory address switches 1 are connected via enabling AND gate 3 to address register 5. The output of the address register is connected via bus 7 to decode matrix 9. Memory address lines indicated conceptually at 11 are also connected, via bus 13, to decode matrix 9. The decode matrix 9 performs a compare function. Without the use of AND 3, a desired memory address can be set into switches 1 and when the desired memory address is reached the output of decode matrix 9 will indicate a comparison and will, via appropriate AND gating circuitry seen, set latch 15 for the stop function. Thus, a program may be made to stop at any address location to which the address register is set. Additionally, the user can select one of several machines cycles identified in the drawing as I1, E1, E2, or E3 which have lines connected to the OR gate 17.

An external input to OR 17 is available to stop the program, thus allowing the operator to use whichever signal is desired or available to him. Further, the central processing unit may be made to stop at various clock times such as T6 or T7 via AND gates 17 and 19, respectively, for such functions as cycle stealing and/or servicing of interrupt cycles. Finally, in contrast to the manual address set via switches 1, automatic setting of the address register may be done via bus 2 using AND 3. Th...