Browse Prior Art Database

Clock Controls for the Microprogram Unit (MPU)

IP.com Disclosure Number: IPCOM000076003D
Original Publication Date: 1971-Dec-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Wong, PC: AUTHOR

Abstract

In data processing systems having a variety of I/O, storage and processing units, it is frequently necessary to suspend operation of one unit while continuing to operate another. When the suspended operation is revived, it must take up at the same point where it was suspended. The asynchronous nature of the interruptions and return to the suspended operation usually require separate clocks and control circuits for each dwell. The circuits shown allow a single clock to drive all units in a system and still accommodate the random timing of the interruptions and returns.

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Clock Controls for the Microprogram Unit (MPU)

In data processing systems having a variety of I/O, storage and processing units, it is frequently necessary to suspend operation of one unit while continuing to operate another. When the suspended operation is revived, it must take up at the same point where it was suspended. The asynchronous nature of the interruptions and return to the suspended operation usually require separate clocks and control circuits for each dwell. The circuits shown allow a single clock to drive all units in a system and still accommodate the random timing of the interruptions and returns.

In a typical system, a series of timing signals are generated having the waveform shown in Fig. 1. Signals 1-6 represent the individual outputs from each stage of a six-position folded ring. The outputs of the ring are logically combined to divide the major ring cycle on three equal length subcycles A, B and
C.

Further decoding is done to generate the timing signals for the control unit and the timing signals for the memory. When the timing signals to the control unit are interrupted to suspend operation, the interruption must occur precisely at the changes from A to B, B to C, C to A, etc. At the same time, the signals to the memory must not be interrupted.

In the circuit shown in Fig. 2, the output signals 1, 2, 3, 4, 5 and 6 from the folded ring are applied to the various AND gates associated with the set inputs to latches 10, 11 and 12. Each AND gate is conditioned by a stop signal and the inhibit signals from the other two triggers. In this fashion, a stop signal is effective to generate an Inhibit A, B or C signal at the first change subsequent to the stop signal.

For example,...