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Digital Filter Synthesizing an All Pass Network Utilizing a Shift Register

IP.com Disclosure Number: IPCOM000076059D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Besseyre, JA: AUTHOR

Abstract

A digital filter as shown in the drawing, is the realization of an all pass network of two poles and two zeros according to the Z plane transfer junction (Hilbert Space): (Image Omitted)

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Digital Filter Synthesizing an All Pass Network Utilizing a Shift Register

A digital filter as shown in the drawing, is the realization of an all pass network of two poles and two zeros according to the Z plane transfer junction (Hilbert Space):

(Image Omitted)

Referring now to Fig. 1, there is shown a logic diagram embodying the general discrete Z plane transfer function H(Z) for a two pole, two zero all-pass network as mapped from the complex frequency plane into the Z plane or (Hilbert Space). A time varying input signal is applied to analog-to-digital converter 1 at the INPUT. As successive digits are propagated through the stages 3, 5, 9, 11 of a shift register, the coefficient multiplication must be performed on the paths 13, 15, 17, 19 connecting the respective stage to the summing network 7. By inserting an appropriate shift left S(-1) and shift right S(+1), logic elements 4, 11, as shown in Fig. 2, it is possible to eliminate the multipliers required in Fig. 1. An alternative placement of the shift elements as depicted in Fig. 3 results also in multiplier elimination.

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