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Browse Prior Art Database

T/2/L Compatible Push Pull Drivers

IP.com Disclosure Number: IPCOM000076065D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Chin, WB: AUTHOR

Abstract

Push-pull driver circuits are provided which operate in a low-power high-performance mode. The push-pull driver can be designed to utilize a relatively low-power supply voltage and to be compatible with the T/2/L circuit family. An illustration of the present circuit is shown in Fig. 1. This circuit is basically a NAND gate circuit with a push-pull output. The circuit is capable of charging or discharging highly capacitive lines. Inputs 10, 11 and 12 are, respectively, applied to both multiple-emitter transistors MT1 and MT2. It should be noted that diodes D1 and D2 are Schottky-barrier diodes. If it is desired to prevent transistors T2 and T3 from being on at the same time, diode D1 may be removed while diode D2 is permitted to remain. Fig. 2 shows another embodiment of the push-pull driver.

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T/2/L Compatible Push Pull Drivers

Push-pull driver circuits are provided which operate in a low-power high- performance mode. The push-pull driver can be designed to utilize a relatively low-power supply voltage and to be compatible with the T/2/L circuit family. An illustration of the present circuit is shown in Fig. 1. This circuit is basically a NAND gate circuit with a push-pull output. The circuit is capable of charging or discharging highly capacitive lines. Inputs 10, 11 and 12 are, respectively, applied to both multiple-emitter transistors MT1 and MT2. It should be noted that diodes D1 and D2 are Schottky-barrier diodes. If it is desired to prevent transistors T2 and T3 from being on at the same time, diode D1 may be removed while diode D2 is permitted to remain. Fig. 2 shows another embodiment of the push-pull driver. In this embodiment, there is a single input 13 applied to diodes D4 and D5. Resistor R3 is equal to resistor R4, but resistor R2 is greater than resistor R1. This will cause transistor T4 to turn off a little later than transistor T5, in order to prevent transistors T5 and T6 from being on at the same time.

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