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Dynamic Binary Word Comparator

IP.com Disclosure Number: IPCOM000076067D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Dimitri, KE: AUTHOR

Abstract

This comparator determines which one of two binary numbers has the larger value. A single bit output is provided giving the result of the sequential comparison of the bits of the binary words.

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Dynamic Binary Word Comparator

This comparator determines which one of two binary numbers has the larger value. A single bit output is provided giving the result of the sequential comparison of the bits of the binary words.

Binary words X and Y are set in parallel into shift registers 1 and 2. The most significant bits X1 and Y1 are set into the first positions of the registers and the least significant bits Xi and Yi are set into the last position of the registers. Under control of clock 3, a bit is shifted from each of registers 1 and 2 to the comparator. Pulses from clock 3 gate ANDs 5 and 6 after passage.by the delay and single-shot block 7. Block 7 prevents glitches from setting latches 8, 9. AND 5 also receives the inverted bit from register 2 and AND 6 receives the inverted bit from register 1.

In the bit-by-bit comparison, if an X bit is greater than a Y bit, latch 8 is set inhibiting latch 9 from setting until it is reset at 10. If a Y bit is greater than an X bit latch 9 is set inhibiting latch 8 from setting until it is reset. If the X and Y bits are equivalent neither of the latches is set. After all of the bits of the X and Y words are compared, the last clock pulse as determined by shift counter 11 gates the results of the comparison through AND Invert 12 to OR 13. Or 13 provides an output at 14 as a logical "1" if the X word is equal to or greater than the Y word. However, if latch 9 has been set by the last significant bit then latch 8 is inhibite...