Browse Prior Art Database

Bit Line to Resistor Configuration

IP.com Disclosure Number: IPCOM000076076D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Lewis, SC: AUTHOR [+2]

Abstract

This is a monolithic memory structure wherein resistors are connected at their opposite ends to bit line diffusion regions.

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Bit Line to Resistor Configuration

This is a monolithic memory structure wherein resistors are connected at their opposite ends to bit line diffusion regions.

Fig. 1 shows the prior art structure. Each of the diffused resistors 1 is connected at its left-hand end to the external metallization 2, which is in turn connected to the bit line diffusion region 3. The right-hand end of each of the resistors 1 is similarly connected to the metallization 4, which is connected to the bit line diffusion region 5.

Fig. 2 shows the arrangement of the subject structure. Each of the diffused resistors la has its left-hand end extended into the bit line diffusion region 3. The right-hand end of each resistor la is similarly extended into the bit line diffusion region 5. This structure saves area of the monolithic chip and provides greater reliability by eliminating the extra contacts.

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