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Transistor Pull Up

IP.com Disclosure Number: IPCOM000076077D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Lewis, SC: AUTHOR

Abstract

This monolithic memory arrangement uses a three-resistor cell for greater stability and less sensitivity to defects. However, greater stability results in harder writing. A pull-up on the resistor word bottom insures writing quickly under worst-case conditions.

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Transistor Pull Up

This monolithic memory arrangement uses a three-resistor cell for greater stability and less sensitivity to defects. However, greater stability results in harder writing. A pull-up on the resistor word bottom insures writing quickly under worst-case conditions.

Requirements of the pull-up are as follows: 1) Until a given voltage difference is established between the rising word top line and the word bottom line, the pull- up should act like a high impedance. 2) After the desired voltage difference is achieved, the pull-up should appear as a low-impedance clamp.

Ideally, a diode fits both requirements. However, one base-emitter voltage drop is too small an offset to be useful. In fact, such a small difference would "pinch" the cell and make disturbs during power-up possible.

The subject pull-up comprises transistor 1 and resistors R1, R2, as shown in Fig. 1. It is desirable to be able to choose the offset. In the pull-up proposed, the offset required before it turns on is VBE (R1 + R2) /R2, where VBE is the base- emitter voltage of transistor 1. The impedance before this voltage is achieved is R1 + R2 and after turning on it is R1/Beta, as shown in Fig. 2.

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