Browse Prior Art Database

Field Effect Transistor and Technique for Making

IP.com Disclosure Number: IPCOM000076081D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Burkhardt, PJ: AUTHOR [+3]

Abstract

The device has SiO(2) as a gate dielectric and a reactively sputtered silicon nitride as a diffusion mask. The two dielectrics are separated by a conductive layer of chromium to prevent charge buildup at the SiO(2)/Si(3)N(4) interface.

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Field Effect Transistor and Technique for Making

The device has SiO(2) as a gate dielectric and a reactively sputtered silicon nitride as a diffusion mask. The two dielectrics are separated by a conductive layer of chromium to prevent charge buildup at the SiO(2)/Si(3)N(4) interface.

The device is fabricated by growing a conventional thick SiO(2) layer 10 on a semiconductor wafer 8, etching a diffusion window 12, as shown in Fig. 1, and subsequently reoxidizing to form a relatively thin layer 11 in opening 12. An aluminum layer 13 having a thickness in the range of 4000 to 5000 angstroms is evaporated on the surface. An overlay of thin SiO(2) or Cr is then deposited and the desired pattern 14 etched, as shown in Fig. 2. A thin coat of Cr is then evaporated which will ultimately form the gate metal. A silicon nitride coating 15 is reactively sputter deposited, the Al removed lifting off the Si(3)N(4), and the source and drain 16 and 18 diffused. This structure is shown in Figs. 3 and 4. Silicon nitride will block diffusion under the gate 20 whereas the thick oxide 10 prevents diffusion anywhere else. A suitable contact metallurgy is then deposited.

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