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Array Logic Implementation of Decoder Check

IP.com Disclosure Number: IPCOM000076114D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Hong, SJ: AUTHOR [+2]

Abstract

An efficient implementation of the decoder check on a memory or an an array logic structure is provided. In the memory, the input address is decoded and the output of the decoder activates exactly one of the rows of the array. The scheme requires the addition of two memory locations per row, such that memory contents are 0,1 if the address has odd parity and 1,0 if the address has even parity. For the example in the Figure, line 1 represents the dot-OR of the memory locations in column 1 and has an output of 1 for addresses with odd parity. Similarly, line 2 has an output of 1 for addresses with even parity. The complement of the error signal is line 1 Exclusive-ORed with line 2.

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Array Logic Implementation of Decoder Check

An efficient implementation of the decoder check on a memory or an an array logic structure is provided. In the memory, the input address is decoded and the output of the decoder activates exactly one of the rows of the array. The scheme requires the addition of two memory locations per row, such that memory contents are 0,1 if the address has odd parity and 1,0 if the address has even parity. For the example in the Figure, line 1 represents the dot-OR of the memory locations in column 1 and has an output of 1 for addresses with odd parity. Similarly, line 2 has an output of 1 for addresses with even parity. The complement of the error signal is line 1 Exclusive-ORed with line 2.

This arrangement can be applied to multidimensional addressing schemes and partitioned logic arrays. It can be used with or without error detecting and correcting codes.

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