Browse Prior Art Database

Double Error Corrections Code with Separable Single Error Correcting Capability

IP.com Disclosure Number: IPCOM000076115D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Hsiao, MY: AUTHOR [+2]

Abstract

The adaptive error correction-code (ECC) system is best illustrated through an example. Assume that the word length of a basic memory unit is 64 data bits, plus 8 check bits for single-error correction double-error correction (SEC-DED). If the double-error correction (DEC) feature is desired, then an additional 7 check bits are required. Since a memory system may have several, say m, basic memory units rather than one, it requires 7 m extra check bits for DEC in the total system. This results in a high cost of implementation and also increases the memory cycle time, even if only a single error has occurred. The adaptive ECC system guarantees the SEC-DED capability on each basic unit and only uses the 7 extra check bits or 8 bits if an overall triple-error detection (TED) capability is required for DEC on the entire system.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 2

Double Error Corrections Code with Separable Single Error Correcting Capability

The adaptive error correction-code (ECC) system is best illustrated through an example. Assume that the word length of a basic memory unit is 64 data bits, plus 8 check bits for single-error correction double-error correction (SEC-DED).

If the double-error correction (DEC) feature is desired, then an additional 7 check bits are required. Since a memory system may have several, say m, basic memory units rather than one, it requires 7 m extra check bits for DEC in the total system. This results in a high cost of implementation and also increases the memory cycle time, even if only a single error has occurred. The adaptive ECC system guarantees the SEC-DED capability on each basic unit and only uses the 7 extra check bits or 8 bits if an overall triple-error detection (TED) capability is required for DEC on the entire system. Single errors are corrected without referring to the additional check bits, hence nominal memory cycle time is not affected. The memory cycle time is increased only in the case of double errors. The H matrix has the following form:

The construction of the submatrices H(64) and A, generated by an APL program, is shown in Fig. 2. The submatrix phi is a null matrix of all zeros.

In the memory system, each word of 64 information bits independently carries 8 check bits which provide the SEC-DED capability on every word separately. Thus, any single error in any word can b...