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Ternary Latches

IP.com Disclosure Number: IPCOM000076125D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Maley, GA: AUTHOR [+2]

Abstract

Two latch circuits are disclosed for three-state operation in the ternary mode. The set input may be raised to a 1 or intermediate voltage level thereby providing a 1 level at the output, which remains latched at that level after the set input is lowered to the O or lower-most level. When the set input is raised to the uppermost or 2 level, the output is set at the 2 level and remains latched at that level when the set input is lowered to the 0 level. The circuits are reset to O by raising the reset input to the 2 level.

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Ternary Latches

Two latch circuits are disclosed for three-state operation in the ternary mode. The set input may be raised to a 1 or intermediate voltage level thereby providing a 1 level at the output, which remains latched at that level after the set input is lowered to the O or lower-most level. When the set input is raised to the uppermost or 2 level, the output is set at the 2 level and remains latched at that level when the set input is lowered to the 0 level. The circuits are reset to O by raising the reset input to the 2 level.

The operation of the circuit of Fig. 1 is as follows. Assume the output is at the lowermost signal level. In this condition transistor T2 conducts two units of current from the transistors T9, T10. One unit of current comes directly from the transistor T10 and the other unit comes from transistor T9 through diode D2. Diode D1 is off and transistor T1 is off. To set a 1 into the latch, that is, to provide that the output be at the intermediate or 1 level, the set input at the base of transistor T5 is raised to a 1 level. This shuts off diode D2 and reduces the current in transistor T2 to one unit of current. If the set input is now dropped to 0, T1 will conduct the current that was formerly flowing through transistor T5, namely one unit, and the latch will store a 1. To set a 2 into the latch the set input is raised to a 2 level. This shuts off transistor T2. Diode D1 now conducts one unit of current to transistor T10. When the set input is returned to 0, transistor T1 will take over conduction from transistor T5 and the latch will store a 2. It should be noted that the set input is capable of raising the output level and that the reset input must be a 0 while the set input is active. The reset input is capable of stepping the latch down to a 0 level. During reset the set input must be at 0.

The reset operation is as follows. Assume that the latch is in a 2 state, then transistor T1 will be conducting two units of current. If the reset input is raised to a 2 level the transistor T8 will conduct, diode D1 will shut off, and the current i...