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Vector Entry Prolog

IP.com Disclosure Number: IPCOM000076132D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 15K

Publishing Venue

IBM

Related People

Jacobs, PC: AUTHOR

Abstract

The IBM System/360 Operating System allows the Access Methods to supply appendage routines to perform functions necessary at IOS time. These functions are: (1) End of Extent (EOE), (2) Start Input/Output (SIO), (3) Program Controlled Interrupt (PCI), (4) Channel End (CE), and (5) Abnormal Channel End (XCE). The Appendage routings are entered from IOS (Input/Output Supervisor) via the Appendage Vector Table (AVT) which is pointed to by a field in the Data Extent Block (DEB). IOS loads an entry (via a vector value of 0, 4, 8, 12, or 16) from the AVT into general register 15 and branches to the appendage via a BALR (Branch and Link) 14, 15 instruction.

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Vector Entry Prolog

The IBM System/360 Operating System allows the Access Methods to supply appendage routines to perform functions necessary at IOS time. These functions are: (1) End of Extent (EOE), (2) Start Input/Output (SIO), (3) Program Controlled Interrupt (PCI), (4) Channel End (CE), and (5) Abnormal Channel End (XCE). The Appendage routings are entered from IOS (Input/Output Supervisor) via the Appendage Vector Table (AVT) which is pointed to by a field in the Data Extent Block (DEB). IOS loads an entry (via a vector value of 0, 4, 8, 12, or 16) from the AVT into general register 15 and branches to the appendage via a BALR (Branch and Link) 14, 15 instruction.

Usually there would be a routine for each type of appendage function. If a common function were necessary, it would exist as code in each appendage. This is wasteful of storage and is not always necessary. To maintain one copy of the common function it is necessary to combine the functions of EOE, SIO, PCI, CE, and XCE into one routine.

Because IOS does not pass the vector value to the appendages, it is difficult to combine common functions into one routine. Several problems develop; (1) base register addressability, (2) technique to "remember" the vector (which function is being called), and (3) how to initialize the AVT properly.

These problems are solved by a method called a VECTOR ENTRY PROLOGUE (VEP). The VEP method is set up as Step 1 Place contiguous Load Address (LA) instructions at the beginning of the common appendage routine. Each LA instruction must load a vector value corresponding to its displacement from the beginning of the appendage routine. The first would load a value of 0, the second a value of 4, the third a value of 8, etc. Step 2 Follow the LA's with a single Execute (EX) instruction to "re-execute" the LA that was initially executed by the BALR from IOS. The EX instruction would use a base register of 15 and a displacement of 0. When the LA instruction is executed the register loaded by the LA instruction will contain the vector entry value. Step 3 Follow the EX instruction with a Subtract Register (SR) instruction. Its purpose is to adjust the base register of the common appendage routine for addressability. The SR instruction would subtract the vector value from the entry point register value. With the VEp method the AVT would be formatted as follows: +0 (address of first LA instruction) address of appendage routine +0 +4 (address, of second LA instruction) address of appendage routine +4 +8 (address of third LA instruction) address of appendage routine +8 +12 (address of fourth LA instruction) address of appendage routine +12 +16 (address of fifth LA instruction) address of appendage routine +16 APPENDAGE VECTOR T:ABLE.

For the Operation System Access Methods, the method of constructing an AVT would be performed by the Open Executors as currently implemented. In several cases a "common appendage...