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Bouncing Switch Output to Single Pulse Converter in Four Phase Logic

IP.com Disclosure Number: IPCOM000076145D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Radzik, LC: AUTHOR

Abstract

Referring to Figure 1, there is shown a four-phase logic arrangement for converting the output of switch S1 into a single pulse at NOR E 23. When switch S1 closes in the ON position 1, the contact tends to bounce. Electrically, the closure and the bouncing are manifest as consecutive pulses. A pulse applied to NAND A 5 will drive the gate into a first stable state. The transition appearing at the output of this gate, will drive NAND B 11 into a second stable state. In turn, the output of gate 11 will maintain gate 5 over path 17 in the first state for a duration exceeding that of the contact bounce.

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Bouncing Switch Output to Single Pulse Converter in Four Phase Logic

Referring to Figure 1, there is shown a four-phase logic arrangement for converting the output of switch S1 into a single pulse at NOR E 23. When switch S1 closes in the ON position 1, the contact tends to bounce. Electrically, the closure and the bouncing are manifest as consecutive pulses. A pulse applied to NAND A 5 will drive the gate into a first stable state. The transition appearing at the output of this gate, will drive NAND B 11 into a second stable state. In turn, the output of gate 11 will maintain gate 5 over path 17 in the first state for a duration exceeding that of the contact bounce.

The four-phase dynamic logic switch to pulse converter takes advantage of the fact that during the set or reset cycle of a four-phase latch, a period of time exists where both sides of the latch will be in the same state. This condition is detected during the set cycle and converted into a single-output pulse.

Referring to Fig. 1 taken together with Fig. 2 assume that the gate 5 consisting of NAND gates 5 and 11 have been reset by a power ON condition so that the output of 5 is a "0" and the output of 11 is a "1". If S1 is now closed (ON) the output of gate 5 will go to 1 the first time a phase two occurs and the input is at a 0 (assume the switch bounces). The input of gate 19 during phase two is at a 1 causing the output of gate 19 to remain at 0 during this four-phase clock cycle. When phase three...