Browse Prior Art Database

I/O Pin Multiplexing with 4 Phase Dynamic Logic

IP.com Disclosure Number: IPCOM000076147D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Campbell, HG: AUTHOR

Abstract

This time multiplexing arrangement, used with four phase-dynamic logic and suitable for mounting on a LSI (large scale integrated) chip, comprises a plurality of remote sending gates 1, 3 coupled to a common output pin through corresponding paths 9, 11. Phase activated gates 13, 15 normally open and, respectively, in series with each path operate to connect a gate 17 to the common output pin. The conventional chip design practice includes an OR gate terminating in the output pin driven by individually phase activated AND gates, the same number of AND gates being required for the receiving chip configuration.

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I/O Pin Multiplexing with 4 Phase Dynamic Logic

This time multiplexing arrangement, used with four phase-dynamic logic and suitable for mounting on a LSI (large scale integrated) chip, comprises a plurality of remote sending gates 1, 3 coupled to a common output pin through corresponding paths 9, 11. Phase activated gates 13, 15 normally open and, respectively, in series with each path operate to connect a gate 17 to the common output pin. The conventional chip design practice includes an OR gate terminating in the output pin driven by individually phase activated AND gates, the same number of AND gates being required for the receiving chip configuration.

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