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User Oriented Subsystem Function Keyboard Logic

IP.com Disclosure Number: IPCOM000076152D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Saxenmeyer, GJ: AUTHOR

Abstract

The keyboard consists of a 5 x 5 matrix of dual-output, momentary-action, solid-state pushbutton switches. The upper-leftmost key is reserved for extraneous use such as an attention signal. The dual outputs of the individual key-cells are 0 volts at rest, nominally +3 volts when operated. The keyboard is expansible to a maximum size of 250 to 500 key-cell positions.

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User Oriented Subsystem Function Keyboard Logic

The keyboard consists of a 5 x 5 matrix of dual-output, momentary-action, solid-state pushbutton switches. The upper-leftmost key is reserved for extraneous use such as an attention signal. The dual outputs of the individual key-cells are 0 volts at rest, nominally +3 volts when operated. The keyboard is expansible to a maximum size of 250 to 500 key-cell positions.

The logic circuit must consistently select the first key depressed when the keyboard has been previously inactive, and positively reject any further keyboard actions for the duration of the ensuing eight-character sequence. To simplify the subject concept into essential form, the keyboard may be considered as generating a specific pair of H1, H2, H3, H4, H5 and V1, V2, V3, V4, V5 concurrent logic-level output signals, which physically designate the respective column and row intersect in the 5 x 5 matrix occupied by the operated key (H1, V1 being excluded by preemption for the ATTN key). This is accomplished by dot-ORing the key-cell outputs by column and by row, to develop "HN" and "VN", respectively. Control Logic.

This logic circuitry is presented schematically in the drawing.

Across the top of the schematic diagram is a chart of the basic keyboard and the five progressive steps of the time-sequenced sweep of the key matrix. It can be seen that the intersection of the concurrent "HN" and "VN" sweeps traverses diagonally downward to the right, in the natural direction of right-handed keyboard fingering faults.

Columns A, B, C, and D on the diagram represent the X Buffer. The Y Buffer, not shown, is a direct replica. The purpose of the buffers is to store the X and Y identity of the operated key for the duration of the eight-character sequence, over a time-span approaching a full second of time duration. The buffers consist of NAND latches, which normally produce a negative ON output, when depicted as shown (if required, the positive output is directly available from the outputs of the column C NAND blocks).

Normal operation is initiated by depression of one of the 24 function keys. This action causes one of the "H" inputs to the 4-way NANDs in column B of the diagram, and one of the counterpart "V"s, to go positive (TTL logical "1's"). As a result, one or two of the five NORs at E-J of row 2 on the diagram will go negative, turning off the 8-way NAND at 6K which is actually functioning as a negative-input OR, going positive at this time. This in turn will de-reset the flip- flops at 2G, 2L, and 6F to 6L, and gate the 1-second single-shot (SS) at 5E to fire during T phi. The OFF output of this single-shot going negative degates the X and Y buffers latch reset, enabling them to latch on when pulsed. Simultaneously, the T phi flip-flop...