Browse Prior Art Database

High Order Zero Print Suppress for Card Punch

IP.com Disclosure Number: IPCOM000076156D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Battistoni, RB: AUTHOR [+3]

Abstract

A buffer 2 holds keyboard entries that are to be applied to a punch and print unit 3 of a card punch. A timing line 4 is energized to signal that buffer 2 is being accessed for transferring data to punch and print unit 3. A latch 5 is connected to be set on the coincidence of a signal on line 4 and a signal on a line 6, which identifies from a program stored in buffer 2 that the first column of a field is being punched. The output 7 of latch 5 is applied to punch and print unit 3 to suppress printing, but to permit punching so long as latch 5 is set.

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High Order Zero Print Suppress for Card Punch

A buffer 2 holds keyboard entries that are to be applied to a punch and print unit 3 of a card punch. A timing line 4 is energized to signal that buffer 2 is being accessed for transferring data to punch and print unit 3. A latch 5 is connected to be set on the coincidence of a signal on line 4 and a signal on a line 6, which identifies from a program stored in buffer 2 that the first column of a field is being punched. The output 7 of latch 5 is applied to punch and print unit 3 to suppress printing, but to permit punching so long as latch 5 is set.

A reset input 8 to latch 5 is energized when a nonzero character is found in the buffer column that is to be punched. The signal on line 8 is developed in time to reset latch 5 to permit printing a nonzero character in the first column of a field. Latch 5 remains reset to permit printing all subsequent zero and nonzero characters of the field.

The circuit also prints a units position zero even though no nonzero character exists in the field. A signal on a line 9 is provided from a program stored in buffer 2 to identify the end of the field. A latch 10 provides appropriate timing to an AND gate 11 for transmitting signal 9 to the reset input of latch 5. Latch 10 is set in response to the signal on line 4 as a character is transferred from buffer 2 to punch and print unit 3, and it is reset a short time later so that it functions to lengthen the signal on line 9 for control...