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Velocity Control for Self Clocked Stepping Motors

IP.com Disclosure Number: IPCOM000076167D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Hendrickson, KE: AUTHOR [+4]

Abstract

Velocity control for self-clocked stepping motors is provided by changing the emitter lead angle. This is accomplished digitally in Fig. 1 by delaying the pulses from emitter 15 to establish a lower limit motor velocity. The upper limit velocity is established by the amplified pulses from emitter 15. The upper and lower limit pulses from amplifier 20 and time delay 20 are applied to AND circuits 40 and 45, respectively. These AND circuits are conditioned by outputs of frequency comparator 30, which compares the frequency of the amplified emitter pulses with the frequency of pulses from reference frequency clock 25. Comparator 30 has an output on line 31 when the reference frequency is greater than the emitter frequency.

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Velocity Control for Self Clocked Stepping Motors

Velocity control for self-clocked stepping motors is provided by changing the emitter lead angle. This is accomplished digitally in Fig. 1 by delaying the pulses from emitter 15 to establish a lower limit motor velocity. The upper limit velocity is established by the amplified pulses from emitter 15. The upper and lower limit pulses from amplifier 20 and time delay 20 are applied to AND circuits 40 and 45, respectively. These AND circuits are conditioned by outputs of frequency comparator 30, which compares the frequency of the amplified emitter pulses with the frequency of pulses from reference frequency clock 25. Comparator 30 has an output on line 31 when the reference frequency is greater than the emitter frequency. For this condition, circuit 45 is rendered active to pass a delayed emitter pulse via OR circuit 50 to motor drivers 55. Motor 10 is thus driven at the lower limit velocity. When the reference frequency is less than the emitter frequency, the comparator 30 provides an output on line 32. This conditions AND circuit 40 and motor 10 is driven at the upper limit frequency. By this arrangement, motor 10 runs at an average velocity of the upper and lower limits.

A more precise velocity control is provided in Fig. 2 by variably delaying the emitter 15 pulse as the emitter pulse frequency changes. Amplified emitter pulses are applied to voltage-control time delay 85. Delay 85 receives an analog- error voltage to either reduce or increase the time delay of t...