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Shift Ring with Shunt Connections for Bypassing Single Stages

IP.com Disclosure Number: IPCOM000076179D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Bliss, BE: AUTHOR [+2]

Abstract

The illustrated shift ring consists of serially coupled registers R associated with respective Load Devices (e.g. data processing units). The registers are coupled for serial shifting of data by normal busses N and bypass busses B. Busses N provide connection paths to successive registers. Busses B provide connection paths to alternate registers, bypassing successive registers. The algorithm for shifting is as follows: 1) Output of each register is coupled to the respective outgoing B and N busses. 2) At tolling of the shift clock (from a not shown clock source common to all registers) input gates in each stage are conditioned to select one of three inputs in the order of priority: a. respective N input bus (if active) b. respective Load Device Output (if active) c.

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Shift Ring with Shunt Connections for Bypassing Single Stages

The illustrated shift ring consists of serially coupled registers R associated with respective Load Devices (e.g. data processing units). The registers are coupled for serial shifting of data by normal busses N and bypass busses B. Busses N provide connection paths to successive registers. Busses B provide connection paths to alternate registers, bypassing successive registers. The algorithm for shifting is as follows: 1) Output of each register is coupled to the respective outgoing B and N busses. 2) At tolling of the shift clock (from a not shown clock source common to all registers) input gates in each stage are conditioned to select one of three inputs in the order of priority: a. respective N input bus (if active) b. respective Load Device Output (if active) c. respective B input bus 3) Input selected at any stage is transferred either directly to the respective Load Device, if the destination address of the transferred information corresponds to the respective stage position, or into the respective register R otherwise.

Thus, under appropriate conditions information is moved around the ring in two-stage shift increments, and since the bypass bus paths are free of active circuits (gates, latches, etc.) at skipped stage positions the delays associated with the propagation of signals through such active circuits are eliminated.

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