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Low Power Latch Decoder

IP.com Disclosure Number: IPCOM000076181D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Platt, S: AUTHOR

Abstract

This circuit consists of a pulse powered TTL decoder driving a silicon-controlled rectifier (SCR) latch. A lateral PNP and vertical NPN transistor form the latch. When the power gate signal is low, no power is supplied to the decoders. The latch is off and the output is low. When the power gate goes high, all but one out of 2N decoders turn on. The selected decoder (i.e. all address inputs high) supplies gate current to the SCR causing it to latch-up (turn on). The output line goes high. Once the selected SCR is latched the power gate signal is returned to its low level, turning off the power to the decoders. In any later cycle, with a different address, the previously latched SCR is reset by its decoder, and a different SCR becomes latched.

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Low Power Latch Decoder

This circuit consists of a pulse powered TTL decoder driving a silicon- controlled rectifier (SCR) latch. A lateral PNP and vertical NPN transistor form the latch. When the power gate signal is low, no power is supplied to the decoders. The latch is off and the output is low. When the power gate goes high, all but one out of 2N decoders turn on. The selected decoder (i.e. all address inputs high) supplies gate current to the SCR causing it to latch-up (turn on). The output line goes high. Once the selected SCR is latched the power gate signal is returned to its low level, turning off the power to the decoders. In any later cycle, with a different address, the previously latched SCR is reset by its decoder, and a different SCR becomes latched. A Schottky diode may be included in the base collector of the decoder to prevent saturation. This circuit reduces substantially the power dissipated in performing a 1 of 2/N/ decode.

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