Browse Prior Art Database

Improved Thick Thin Oxide Threshold Ratio

IP.com Disclosure Number: IPCOM000076183D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Siegle, WT: AUTHOR

Abstract

This method allows improvement between the thick and thin oxide threshold ratio of FET integrated circuits, without utilizing extremely thick oxides between active devices.

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Improved Thick Thin Oxide Threshold Ratio

This method allows improvement between the thick and thin oxide threshold ratio of FET integrated circuits, without utilizing extremely thick oxides between active devices.

The process includes the steps of depositing a layer 12 of an appropriately doped oxide on semiconductor substrate 10. The type of dopant present in oxide 12 is dependent upon whether p- or n- channel FET devices are to be fabricated. Active device regions are then delineated by etching through a photoresist mask, not shown. A high temperature drive-in and reoxidation follows to provide diffused regions 14 in the nondevice areas and clean oxide layer 16. Subsequent processing includes fabrication of active devices, for example self-aligned silicon gate n-channel FET. The threshold of the active devices is determined by the undoped oxide layer 16 and the original doping level of substrate 10. The thick oxide threshold is controlled by the resulting thick oxide thickness and the doping level resulting from the drive-in of impurities from oxide source 12.

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