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Optimization of Fault Simulation by Preanalysis

IP.com Disclosure Number: IPCOM000076205D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Vogelsberg, RE: AUTHOR

Abstract

Fault simulation of logic devices and systems is a vital component in the development of effective manufacturing tests and field diagnostics. Programmed fault simulation is expensive due to the large amount of computer running time required.

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Optimization of Fault Simulation by Preanalysis

Fault simulation of logic devices and systems is a vital component in the development of effective manufacturing tests and field diagnostics. Programmed fault simulation is expensive due to the large amount of computer running time required.

A number of programmed fault simulation scheduling algorithms exist which can provide zero-delay, unit-delay, and variable-delay simulation modes. In the order listed, these simulation modes provide increasing precision with respect to logic delays in return for increasing simulation running time. Fault simulation running time can be minimized if the simulation mode used and the delays within that mode are the least precise necessary to provide sufficient accuracy in the output data. A preanalysis based upon a series of good-machine simulations is used to select the least precise acceptable fault simulation mode.

The selection procedure is based upon repetitive good-machine simulations, to determine the minimum amount of simulator precision required to provide sufficient fault simulation accuracy. Initially a good-machine simulation is performed to the maximum available precision to establish the correct nonfailing logic responses. During this simulation the logic output status is recorded for each input test sequence as follows: 1) If the logic is being tested in a static mode (i.e. the results of each input change are allowed to stabilize and the output values checked before another change is made), the time and the value at which each output stabilizes is recorded. 2) If the logic is being tested in a dynamic mode (i.e. the input changes are made at logic operating speed and the output values sampled at specified times with the cycle), the values of the outputs are recorded at each sampling point.

Once the correct logic responses have been determined, good-machine simulations are made using less precise simulation modes to select the fault simulation operating mode.

The first such simulation may be a two-value zero-delay simulation. If the results of this simulation agree with the previously determined correct logic responses, the two-value zero-delay fault simulation mode is used. If the results do not agree, the unit-delay stage of good-machine simulation is tried. The two- value zero-delay simulation may be omitted in cases involving sequential logic or a dynamic testing procedure, because of the known limitations of the simulation mode.

The second good-machine simulation stage uses a three-value unit-delay simulation. The average of the precise logic delays is selected as the unit of...