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Identifying Sources of Unknown Levels Generated during Three Value Fault Simulation

IP.com Disclosure Number: IPCOM000076206D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 15K

Publishing Venue

IBM

Related People

Vogelsberg, RE: AUTHOR

Abstract

The fault simulation of digital logic is often done with a three-value (1, 0, and X) mode of simulation. The third value (X) is used to represent initially unspecified internal logic status and unknown input values. The third value may also be used to detect timing hazards. Use of the third value prevents the generation of erroneous results during simulation (i.e. the simulator will set indeterminant logic values to X rather than 1 or 0). Unfortunately, the occurrence of an unknown output value serves only to detect a potential problem. Further analysis of the test sequence and logic is required to resolve the actual hardware behavior.

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Identifying Sources of Unknown Levels Generated during Three Value Fault Simulation

The fault simulation of digital logic is often done with a three-value (1, 0, and
X) mode of simulation. The third value (X) is used to represent initially unspecified internal logic status and unknown input values. The third value may also be used to detect timing hazards. Use of the third value prevents the generation of erroneous results during simulation (i.e. the simulator will set indeterminant logic values to X rather than 1 or 0). Unfortunately, the occurrence of an unknown output value serves only to detect a potential problem. Further analysis of the test sequence and logic is required to resolve the actual hardware behavior.

During fault simulation an unknown level may be generated by a simulated error that prevents a latch from being initially reset, or that creates a race condition or oscillation that sets a latch to the unknown level. An automated procedure is developed to resolve the ambiguity detected by the unknown value. The resolution required is the ability to determine if a failure, that has been detected at an unknown level (X) during simulation, will be detected by the hardware test device at a known level (1 or 0). To provide such resolution, it is required that the source of the unknown value and the path through which the unknown was propagated to the final logic outputs be identified.

The following procedure will provide the required identification. An additional fault simulation is performed for failures detected only at the unknown level. During this simulation an All Events Trace of the activity caused by the failure is written.

Following the simulation, a backtrace of the All Events Trace is performed to identify the source of the unknown value and the paths through which the unknown was propagated to the outputs.

Initially a normal fault simulation of all the selected failures is performed. During this fault simulation a list of all the failures that were detected only with the unknown value is prepared. This list is used as input to subsequent fault simulations. For each failure on the list of a fault simulation is performed and a failure All Events Trace (AET) is written. The AET contains records for every logic block that was calculated during the simulation and changed value because of the failure. Records are also kept during the fault simulation of the times and final outputs at which the failure was detected.

Following the fault simulations a backtrace is performed for each failure using the failure AET. The backtrace begins at the times and outputs at which the failure was detected. Each output block identification and time is used to locate the corresponding entry on the failure AET. The input data in the failure AET record is then used to locate subsequent AET records. The effect of this procedure is to trace the propagation of the unknown value backwards in time and through the logic, until the source of t...