Browse Prior Art Database

Programmable Digital Comparator

IP.com Disclosure Number: IPCOM000076216D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Elliott, JC: AUTHOR [+2]

Abstract

Go-no-go scanning is usually instrumented in the central processing unit (CPU) of a computer on a compare basis or on an interrupt on fail basis. This requires interrupt service routines for support. When multiple limit compares are performed they are done serially. This programmable comparator provides for a simultaneous double-ended comparison and the ability to cycle-steal fail or pass data into storage without interruption of the main line program.

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Programmable Digital Comparator

Go-no-go scanning is usually instrumented in the central processing unit (CPU) of a computer on a compare basis or on an interrupt on fail basis. This requires interrupt service routines for support. When multiple limit compares are performed they are done serially. This programmable comparator provides for a simultaneous double-ended comparison and the ability to cycle-steal fail or pass data into storage without interruption of the main line program.

The comparator includes a data register 1 coupled to a cycle-steal channel 2 which is coupled to CPU 3 of a computer. The data is introduced to register 1 on a cycle-steal basis from channel 2 or from an external device 8, such as a digital voltmeter or an analog to digital converter. Limits are programmed from channel 2 in four-limit registers 4. Through gates controlled by command decode 5, the limits in registers 4 and buffered data in register 1 are coupled to combinatorial full adder 6. The buffered data is first acted on in a two's complementer 7, which is triggered by a program command from command decode 5 or an external sync line.

Each comparison made in adder 6 is against a pair of high/low limits for one of the specified two ranges. Under program control, the reporting back to CPU 3 through channel 2 and connection 9 may consist of the data itself provided from register 10. The decoded results from the comparison in adder 6, after decoding at 11, are provided in pass, fail...