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Analog Hold Shift Register Stage

IP.com Disclosure Number: IPCOM000076226D
Original Publication Date: 1972-Jan-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

van Tol, WC: AUTHOR

Abstract

This is a delay mechanism for analog signals of arbitrary shape and amplitude. The difference between an input signal and an output signal is a function of the number of storage elements traversed and the clock frequency. At regular intervals, samples of the momentary signal are taken by clock pulses and shifted at the same rate through the register. The bandwidth is determined by the clock frequency. The delayed signal may be read out at the output of every element.

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Analog Hold Shift Register Stage

This is a delay mechanism for analog signals of arbitrary shape and amplitude. The difference between an input signal and an output signal is a function of the number of storage elements traversed and the clock frequency. At regular intervals, samples of the momentary signal are taken by clock pulses and shifted at the same rate through the register. The bandwidth is determined by the clock frequency. The delayed signal may be read out at the output of every element.

A read strobe at the base of transistor T1, resulting from a positive transition of clock pulse train X, renders T1, conductive, which makes node A negative. Consequently, T2 and T3 may conduct for the duration of the read strobe.

As long as the voltage at the base of T4 exceeds the voltage at the base of T5, T4 conducts, which causes T6 to conduct, so that node B is made positive and T7 conducts, through which capacitor C1 is discharged until the potential thereover equals the input voltage at the base of T4. Node B, being positive, prevents T8 from conducting. When the base voltage of T5 exceeds (less negative) that of T4, capacitor C1 is charged through T8 in a negative sense until the voltage thereover equals the voltage at the base of T4. Regardless of fluctuations in the supply voltages or the clockpulse amplitudes, the voltage developed over the output capacitor will always exactly equal the input voltage.

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