Browse Prior Art Database

Surface Controlled Semiconductor Arrangement

IP.com Disclosure Number: IPCOM000076263D
Original Publication Date: 1972-Feb-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Remshardt, R: AUTHOR [+2]

Abstract

This is a one-device storage cell having improved stability in each of its bistable storage states.

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Surface Controlled Semiconductor Arrangement

This is a one-device storage cell having improved stability in each of its bistable storage states.

The storage cell comprises, as shown in Figs. 1 and 2, a body 10 of P-type semiconductor material, having therein diffused N-type source and drain regions 11 and 12. A thin oxide layer 14 covers the region 15 existing between the source 11 and drain 12 and a gate electrode 16 overlies this oxide layer 14. P doped polycrystalline semiconductor material is used for the gate electrode 16 and for the source and drain connections 17 and 18. Two additional N-type diffusions 19 and 20 are also existing in body 10. Region 19 is created within the region 15 existing the source 11 and drain 12, while region 20 is outside this region 15. Direct connections 21 and 22 are made between regions 10 and 20 and the gate 16.

The connections 21 and 22 between gate 16 and regions 19 and 20 are designed as Schottky barrier diodes. When using the above arrangement as a storage cell, one storage cell; e.g., the "1" state is characterized by a conductive channel between source and drain regions and the other state; e.g., "0" state is characterized by the absence of a channel between the source and drain regions. Thus when a positive pulse is applied to the gate 16 and an N-type channel is formed between the source and drain regions, the potential distribution change along the created channel is tapped, via connection 21 and region 19, causing th...