Browse Prior Art Database

Dynamic Mode Latent Image Memory

IP.com Disclosure Number: IPCOM000076270D
Original Publication Date: 1972-Feb-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Ho, IT: AUTHOR

Abstract

This is a latent-image memory cell configuration for dynamic random-access memories.

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Dynamic Mode Latent Image Memory

This is a latent-image memory cell configuration for dynamic random-access memories.

In the drawing, a three-device field-effect transistor (FET) dynamic random- access memory cell consisting of transistors T1, T2 and T3 is shown. A latent- image memory (LIM) which is basically a read-only memory (ROM) superimposed on a random-access memory (RAM) is implemented by adding transistor T4. As shown, T4 shares both the source and drain diffusions of T3 saving monolithic chip area. The ROM is personalized by connecting or not connecting the gate of T4 to the additional LIM line. In order to read the information stored in the ROM, a 0 should first be written into the cell. The 0 is arbitrarily defined as the condition when T3 is turned off. A pulse is then sent through the LIM line. If T4 is connected to the LIM line, then it will be turned on to represent a "1" in the ROM. If the gate of T4 is not connected to the LIM line, then T4 cannot be turned on. A typical waveform diagram is shown in Fig. 2.

In order to implement this LIM concept in a one-device FET cell, see Fig. 3. In the one-device cell, T1 is the original cell and T4 provides the latent image. 1's and 0's are distinguished by whether the gate of T4 is connected or not to the LIM line.

The advantage of the present circuit is not only in incorporating both RAM and ROM on the same chip, but also the implementation of a LIM in a dynamic cell. The decoder, sensing, and driving cir...