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Detecting Defects in Integrated Semiconductor Circuits

IP.com Disclosure Number: IPCOM000076280D
Original Publication Date: 1972-Feb-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Hubacher, EM: AUTHOR [+2]

Abstract

Integrated semiconductor circuits are produced by conventional photolithographic fabrication techniques. The diffusion steps and metallization interconnection steps on the integrated circuits are carried out by such techniques. It has been customary practice to use visual or optical inspection techniques for detecting errors in either diffusion or metallization steps. However, with the ever increasing density of integrated circuits, such visual or optical inspection is becoming less feasible.

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Detecting Defects in Integrated Semiconductor Circuits

Integrated semiconductor circuits are produced by conventional photolithographic fabrication techniques. The diffusion steps and metallization interconnection steps on the integrated circuits are carried out by such techniques. It has been customary practice to use visual or optical inspection techniques for detecting errors in either diffusion or metallization steps. However, with the ever increasing density of integrated circuits, such visual or optical inspection is becoming less feasible.

There is here provided an approach which uses electrical monitoring for the detection of such defects in place of the visual or optical inspection techniques. Electrical test devices are placed in the wafer kerf, i.e., the parallel regions on the wafer between the chips, which regions are cut away during dicing. The tests are carried out on the wafer between the various fabrication steps.

The device in Fig. 1 is used for determining whether contact holes C1, C2 and C3, through protective oxide layer 10 to P type resistor 11 (see Fig. 2) in substrate 12 have been made. Metallization 13 makes the contacts shown to the substrate through contact holes C1, C2 and C3, as will as contact holes 14 and
15. The resistance of P type resistor 11 between each adjacent contact hole is the same, namely, a value of R. Accordingly, if the total resistance between contacts 14 and 15 is measured, it will only have a value of R if all the contacts are good. On the other hand, it will have the following values indicative of contacts being bad in accordance with the listing below: Resistance Value Bad Contacts 2R C3 3R C2 and C3 4R C1, C2 and C3.

In Fig. 3, there is shown another device for determining whether the various diffusion steps have been carried out properly. The device, shown in plan view in Fig. 3, is a standard semiconductor formed in an N type epitaxial layer over an N+ subcollector region which has a P+ surrounding insulation diffusion, a P base and an N+ emitter. The N epitaxial layer serves as the collector region. The device is covered by an insulative layer, such as silicon dioxide, through which contact holes 1-6 are...