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Nonlinear Timer

IP.com Disclosure Number: IPCOM000076287D
Original Publication Date: 1972-Feb-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Norris, GH: AUTHOR [+2]

Abstract

This timer is capable of timing intervals ranging from microseconds to minutes with the same degree of accuracy. Feedback gating is used to achieve a quasi-logarithmic time scale.

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Nonlinear Timer

This timer is capable of timing intervals ranging from microseconds to minutes with the same degree of accuracy. Feedback gating is used to achieve a quasi-logarithmic time scale.

A 100KHz clock 10 is connected to increment 4-stage counter 11 at a rate selected by one of the frequency dividers 12-16. Upon counter 11 counting to sixteen, a count is advanced into 5-stage counter 17 and feedback gating on conductors 18 selects a higher-order frequency divider to increment counter 11 for the next sixteen counts.

As shown, frequency divider 12 divides by two; divider 13 divides by four; divider 14 divides by sixteen, and so on.

Upon the occurrence of an interval to be timed, the clock 10 is turned on and the first sixteen counts advance into counter 11 through AND gates 19-23 at a 100KHz rate. At the sixteenth cycle of the 100KHz signal, a count is entered into the first bit-position 24 of counter 17. As a result, an output on conductor 25 changes the gating such that the 100KHz clock output must now pass through AND gates 19-22 and through divide-by-two frequency divider 12 to AND gate
26. For the next sixteen counts of counter 11 the counter increments at a 50KHz rate.

In like fashion, at the end of the second series of sixteen counts of counter 11, a count advances into counter 17 and the feedback gating again changes to require that the 100KHz clock output advance into counter 11 at a 25KHz rate, through AND gates 11-21, frequency divider 13, and A...