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Dynamic MOSFET Multipurpose Flip Flop

IP.com Disclosure Number: IPCOM000076304D
Original Publication Date: 1972-Feb-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Kirby, MD: AUTHOR

Abstract

The four-phase dynamic metal-oxide silicon field-effect transistor (MOSFET) circuit shown contains a minimum number of FET devices, yet can be connected to provide nine different bistable functions as shown in the table. The circuit operates using four-phase nonoverlapping clock signals 1 through 4, which appear at labeled terminals within each logic gate. A bit time is the time required for all four nonoverlapping clock phases to occur. The multipurpose flip-flop stores a data bit by recirculating the data bit within the flip-flop, once each bit time. Input signals (at the proper phase times) A, B, C, D, and E, control recirculation. Inputs A and D must be available during phase 2 time. Inputs C, D, and E, must be available during phase 3 time. Outputs are provided at terminals F, G, H, and I.

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Dynamic MOSFET Multipurpose Flip Flop

The four-phase dynamic metal-oxide silicon field-effect transistor (MOSFET) circuit shown contains a minimum number of FET devices, yet can be connected to provide nine different bistable functions as shown in the table. The circuit operates using four-phase nonoverlapping clock signals 1 through 4, which appear at labeled terminals within each logic gate. A bit time is the time required for all four nonoverlapping clock phases to occur. The multipurpose flip-flop stores a data bit by recirculating the data bit within the flip-flop, once each bit time. Input signals (at the proper phase times) A, B, C, D, and E, control recirculation. Inputs A and D must be available during phase 2 time. Inputs C, D, and E, must be available during phase 3 time. Outputs are provided at terminals F, G, H, and I. The basic output appears at terminal F, and is available at phase times 4 and 1. The logical function of F is F = E ((A + B) (C + D)). The outputs G, H, and I, are delayed inversions of the basic output F. G equals F and is available phase times 1 and 2. H equals F and I equals F. H and I are available at phase times 2 and 3.

The basic output signal at F is implemented by gates 11, 12 and 13. During phase 1 time, the output node 21 of NOR gate 11 is unconditionally precharged through transistor T1. At phase 2 time, transistor T2 is rendered conductive to conditionally discharge node 21 in accordance with the signals at terminals A and ...