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Common Emitter Resistor for Monolithic Memory Cells

IP.com Disclosure Number: IPCOM000076318D
Original Publication Date: 1972-Feb-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Vogl, NG: AUTHOR

Abstract

Latch-type monolithic memory cells can have reduced sensitivity to leakage current and noise signals, if a resistor is used in the emitter lead of each cell. A power addressed monolithic memory cell comprises a transistor pair Q1 and Q2, each having a common base and common collector which is cross coupled to a second pair of transistors Q3 and Q4, which also have common bases and common collectors. These cross coupled transistor pairs thus form a bistable circuit. Load resistors R1 and R2 for each of the semiconductor devices are interposed between the word top and the collector of the respective transistor pairs. The emitter of transistor Q1 is connected to a first bit-sense line B/S1. The emitter of transistor Q4 is similarly coupled to a second bit-sense line B/S2.

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Common Emitter Resistor for Monolithic Memory Cells

Latch-type monolithic memory cells can have reduced sensitivity to leakage current and noise signals, if a resistor is used in the emitter lead of each cell. A power addressed monolithic memory cell comprises a transistor pair Q1 and Q2, each having a common base and common collector which is cross coupled to a second pair of transistors Q3 and Q4, which also have common bases and common collectors. These cross coupled transistor pairs thus form a bistable circuit. Load resistors R1 and R2 for each of the semiconductor devices are interposed between the word top and the collector of the respective transistor pairs. The emitter of transistor Q1 is connected to a first bit-sense line B/S1. The emitter of transistor Q4 is similarly coupled to a second bit-sense line B/S2. The emitters of transistors Q2 and Q3 are coupled together and through a common emitter resistor RE to the word bottom.

This resistor RE, in series with the emitters of transistors Q2 and Q3, reduces sensitivity of the cell to capacitive noise coupled from bit lines. It also permits the greater signal degradation due to leakage, and still further reduces the sensitivity of the cell due to leakage by a greater amount than an equal resistor in the collector load.

When the cell is operating at high-current levels, the emitter resistor RE is automatically switched out of the circuit and thus does not contribute to the word top voltage.

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