Browse Prior Art Database

Field Effect Transistor Memory

IP.com Disclosure Number: IPCOM000076344D
Original Publication Date: 1972-Feb-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Kruggel, R: AUTHOR

Abstract

This memory employing one-device cells has array interconnections, which reduce load or line capacitance by a factor of about two. The cells require only word lines 10, 12 and bit/sense lines 14 without the need for conventional ground lines, as, for example, utilized in the one-device cell arrangement described in U.S. Patent 3,387,286, by using unselected word lines 10, 12 for grounds to minimize the line capacitance and the cell area.

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Field Effect Transistor Memory

This memory employing one-device cells has array interconnections, which reduce load or line capacitance by a factor of about two. The cells require only word lines 10, 12 and bit/sense lines 14 without the need for conventional ground lines, as, for example, utilized in the one-device cell arrangement described in U.S. Patent 3,387,286, by using unselected word lines 10, 12 for grounds to minimize the line capacitance and the cell area.

The line capacitor CL is composed of a diffusion and gate-to-drain capacitance and the storage capacitors CS1 and CS2 are an enhanced source- to-ground capacitance.

The array, for purposes of illustration, has two devices, FET transistor T1 and FET transistor T2, with their associated storage capacitors CS1 and CS2 forming two random-access storage cells A and B. Information is stored into selected cells A or B by charging capacitor CS1 or CS2 through its transistor, and information is read out by discharging the capacitor through the transistor. To write into, for example, cell A, the word line 10 is energized, by word line driver 16, to render T1 conductive between source and drain. Capacitor CS1, which is grounded through unselected word line 12 and word line driver 16, is then charged by a pulse from bit line driver and sense amplifier 18 through bit line 14 and T1. If a 0 is to be stored, bit line 14 is grounded to discharge capacitor CS1. During read operations, only the word line of the selec...