Browse Prior Art Database

Fetch/Store Link Mechanism

IP.com Disclosure Number: IPCOM000076352D
Original Publication Date: 1972-Feb-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Anderson, DW: AUTHOR [+4]

Abstract

In high-performance pipelined machines a number of storage requests can be outstanding at any given point in time. The link mechanism described provides for the logical order of these requests, when necessary.

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Fetch/Store Link Mechanism

In high-performance pipelined machines a number of storage requests can be outstanding at any given point in time. The link mechanism described provides for the logical order of these requests, when necessary.

Linking of requests to storage is required to preserve logical correctness of transactions made to a common storage location. They invariably spring from the fact that (a) a store address generally precedes its associated data into the Storage Control Unit (SCU) and (b) it is possible that a number of subsequent addresses will be received by the SCU prior to the store data becoming available. It is in order to retain high performance and yet cope with the link problem that the Store Address Registers (SARs) and Fetch Address Registers (FARs) have been postulated in a SCU, such as disclosed in U. S. Patent 3,449,723. A straightforward and not excessively expensive technique through which links are established and released between SARs and FARs is illustrated here. The diagram shows the data path which concerns this mechanism. SAB 1 - (storage address bus) bus on which double word storage addresses appear for fetch or store requests SAB FETCH 2 i control line to indicate storage fetch request SAB STORE & ID 3 - control lines to indicate storage store request and assigned SAR ID SAR 4 - (storage address registers) three registers in the SCU to hold store addresses, until the store data is available to cause a "put away" into the storage system FAR 5 - (fetch address registers) three registers in the SCU to hold fetch addresses until the fetch operation can be completed. These are loaded when a fetch request from the Central Processing Unit (CPU) cannot be completed due to a "linking" condition. SAR & FAR Valid Bits 6 - valid bits are present on all SARs and FARs to indicate when its contents should be actively compared with new addresses being presented on SAR. Note: For store operations the CPU directs the store address into a preassigned SAR. For fetch operations the SCU will assign a...